The present invention relates to MOS devices and, more particularly, to an improved trench MOS gate device and a process for forming same.
An MOS transistor that includes a trench gate structure offers important advantages over a planar transistor for high current, low voltage switching applications. In the latter configuration, constriction occurs at high current flows, an effect that places substantial constraints on the design of a transistor intended for operation under such conditions.
A trench gate of a DMOS device typically includes a trench extending from the source to the drain and having sidewalls and a floor that are each lined with a layer of thermally grown silicon dioxide. The lined trench is filled with doped polysilicon. The structure of the trench gate allows less constricted current flow and, consequently, provides lower values of specific on-resistance. Furthermore, the trench gate makes possible a decreased cell pitch in an MOS channel extending along the vertical sidewalls of the trench from the bottom of the source across the body of the transistor to the drain below. Channel density is thereby increased, which reduces the contribution of the channel to on-resistance. The structure and performance of trench DMOS transistors are discussed in Bulucea and Rossen, xe2x80x9cTrench DMOS Transistor Technology for High-Current (100 A Range) Switchingxe2x80x9d in Solid-State Electronics, 1991, Vol. 34, No. 5, pg. 493-507, the disclosure of which is incorporated herein by reference. In addition to their utility in DMOS devices, trench gates are also advantageously employed in insulated gate bipolar transistors (IGBTs), MOS-controlled thyristors (MCTs), and other MOS gated device structures.
Trenches lined with oxide dielectric and filled with polysilicon as a means of providing lateral isolation for component islands situated within the trench regions are described in U.S. Pat. Nos. 5,196,373 and 5,248,894, the disclosures of which are incorporated herein by reference. A preferred method of forming the dielectric for this purpose is conventional thermal oxidation.
Thermal oxidation to produce silicon dioxide for isolation of component islands does not require the control of oxide layer thickness provided by the device and process of the present invention. The dielectric used for isolation is very thick, often thicker than 10,000 angstroms. In this thickness range, the oxide grows according to a parabolic growth rule that produces the same growth rate on all crystal surfaces rather than by the orientation dependent linear growth rate that applies to the hundreds of angstroms thickness range relevant for gate oxides. Consequently, thermally grown oxides for isolation purposes have essentially the same thickness on all surfaces.
To minimize oxidation induced stress, a thin, approximately 100-angstrom thick thermal oxide layer is sometimes grown to cover an island surface. This thin oxide layer is then covered with a thick deposited oxide layer of about 10,000 angstroms to provide the required isolation. In such instances, the isolation layer consists almost entirely of deposited oxide. This layer must be thick enough to ensure that average capacitance is low and that the oxide rupture voltage is higher than the maximum voltage to be isolated. However, there are no minimum thickness or uniformity constraints for oxide layers intended for isolation of component islands.
Although the trench gate structure is beneficial for the operation of a transistor at higher currents, its performance can be degraded by the formation of a gate-to-drain capacitance across the dielectric material in the bottom of the trench. Furthermore, the bottom corners of the trench can cause concentration of an electric field when the DMOS is reverse biased, resulting in reduced breakdown voltage. These effects can be mitigated by beneficially controlling the formation of the dielectric layers on the sidewalls and floor of the gate trench, which is provided by the present invention.
The present invention is directed to an improved trench MOS gate device that comprises a trench whose floor and sidewalls include layers of dielectric material, the layers each having a controlled thickness dimension. These thickness dimensions are related by a controlled floor:sidewall layer thickness ratio, which is established by individually controlling the thickness of each of the floor and sidewall dielectric layers. This floor to sidewall layer thickness ratio is preferably at least 1 to 1, more preferably at least 1.2 to 1.
Further in accordance with the present invention, a process for forming an improved trench MOS gate device comprises etching a trench in a silicon device wafer and forming layers of dielectric material on the trench floor and on the sidewalls, each layer having a controlled thickness dimension. The thickness dimensions are related by a controlled floor to sidewall layer thickness ratio that is preferably at least 1 to 1. When silicon dioxide is employed as the dielectric material, the layers preferably comprise a composite of thermally grown and deposited silicon dioxide.
The trench containing the dielectric layers is filled with polysilicon, and an insulator layer is formed over the polysilicon, thereby forming a trench gate. A patterned electrically conducting metallic interconnect is formed over the trench gate.
The improved trench MOS gate device of the present invention includes a trench gate having a trench provided with layers of dielectric material of an advantageously controlled thickness ratio on the floor and the sidewalls, which reduces the damage caused by undesirable parasitic effects.